1. Field of the Invention
This invention generally pertains to semiconductor processing, and, more particularly, to the polishing of process layers formed above a semiconducting substrate.
2. Description of the Related Art
The manufacture of semiconductor devices generally involves the formation of various process layers, selective removal or patterning of portions of those layers, and deposition of additional process layers above the surface of a semiconducting substrate. The substrate and the deposited layers are collectively called a xe2x80x9cwafer.xe2x80x9d This process continues until a semiconductor device is completely constructed. The process layers may include, by way of example, insulation layers, gate oxide layers, conductive layers, and layers of metal or glass, etc. It is generally desirable in certain steps of the wafer fabrication process that the uppermost surface of the process layers be approximately planar, i.e., flat, for the deposition of subsequent layers. The operation used to produce an approximately flat, uppermost surface on a wafer is called xe2x80x9cplanarization.xe2x80x9d
One planarization operation is known as xe2x80x9cchemical-mechanical polishing,xe2x80x9d or xe2x80x9cCMP.xe2x80x9d In a CMP operation, a deposited material is polished to planarize the wafer for subsequent processing steps. Both insulative and conductive layers may be polished, depending on the particular step in the manufacturing process. For instance, a layer of metal previously deposited on the wafer may be polished with a CMP tool to remove a portion of the metal layer to form conductive interconnections such as metal lines and plugs. The CMP tool removes the metal process layer using an abrasive action created by a chemically active slurry and a polishing pad. A typical objective is to remove the metal process layer down to the upper level of the insulative layer, but this is not always the case.
The point at which the excess conductive material is removed and the embedded interconnects remain is called the xe2x80x9cendpointxe2x80x9d of the CMP operation. CMP tools use optical reflection, thermal detection, and/or friction-based techniques to detect the endpoint. The CMP operation should result in a planar surface with little or no detectable scratches or excess material present on the surface. In practice, the wafer, including the deposited, planarized process layers, are polished beyond the endpoint (i.e., xe2x80x9coverpolishedxe2x80x9d) to ensure that all excess conductive material has been removed. Excessive overpolishing increases the chances of damaging the wafer surface, uses more of the consumable slurry and pad than may be necessary, and reduces the production rate of the CMP equipment. The window for the polish time endpoint can be small, e.g., on the order of seconds. Also, variations in material thickness may cause the endpoint to change. Thus, accurate in-situ endpoint detection is highly desirable.
Furthermore, a CMP tool typically polishes several, sometimes as many as five, wafers at the same time. Variations and tolerances in the manufacturing process create variations in the wafers. Frequently, one or more wafers will be polished to the endpoint while the others are not. Conventional CMP tools, however, must polish all the wafers for the same length of time. This is true, even though optical reflection, thermal detection, and friction based data may indicate one or more of the wafers are at the endpoint. Consequently, when the CMP tool halts the operation, the wafers will be at varying stages ranging from very overpolished to underpolished. If a particular CMP tool continually underpolishes or excessively overpolishes at one of its stations, it can be manually adjusted. More particularly, the CMP tool can be taken out of a process flow, tested, manually adjusted, and re-introduced into the process flow.
This particular problem is not limited to CMP tools. Many kinds of processing tools include multiple workstations performing identical operations at different rates. Among these types of tools are, for instance, multi-chamber etchers. Etching is an extremely common operation used to selectively remove portions of layers on a wafer. An etcher typically includes several etching chambers. As with the multi-station CMP tool, wafer-to-wafer variations may be encountered because of the etcher""s operation. These variations in etching rates injects still further variation into the manufacturing process, thereby decreasing yields.
The present invention is directed to a semiconductor processing method and apparatus that solves, or at least reduces, some or all of the aforementioned problems.
The invention includes a technique for processing a wafer in a semiconductor manufacturing process are disclosed. In one aspect, a method comprises first collecting a set of processing rate data from a multi-station processing tool, the set including process rate data from at least two stations in the processing tool. The collected processing rate data is then communicated to a controller that autonomously compares the processing rate data to determine whether to adjust a process parameter. The method then adjusts the process parameter for at least one station to match the process endpoint for the at least one station. In other aspects, the invention includes a program storage medium encoded with instructions to perform the method and a computing device programmed to perform the method.